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Rev 0; 10/08
DDR Clock Oscillator
General Description
The DS4266 surface-mount ceramic crystal oscillator is part of Maxim's DS4-XO crystal oscillator product family. The DS4266 is a 266MHz crystal oscillator designed to support high-performance DDR memory applications that require a stable, low-jitter, and tight duty-cycle clock source. The device provides an overall accuracy and stability better than 50ppm, including aging. Jitter performance is better than 0.7psRMS typically over a 12kHz to 20MHz bandwidth, and duty-cycle performance is better than 48%/52%. The DS4266 has an output frequency of 266MHz, and it supports LVDS and LVPECL output types. The DS4266 is constructed using a fundamental crystal in conjunction with high-performance silicon germanium PLL technology, enabling very low phase noise and phase jitter performance. The device operates from a 3.3V 5% power supply and consumes a maximum current of 100mA. The DS4266 is packaged in a miniature 5mm x 3.2mm x 1.49mm, 10-lead LCCC ceramic package, making it suitable for applications where board space is critical.
Features
< 0.7psRMS (typ) from 12kHz to 20MHz Jitter LVDS or LVPECL Output Types 3.3V Operating Voltage 5.0mm x 3.2mm x 1.49mm, 10-Pin LCCC Ceramic Package -40C to +85C Operating Temperature Range Lead-Free/RoHS Compliant
DS4266
Ordering Information
PART DS4266D+ DS4266P+ TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 10 LCCC 10 LCCC
+Denotes a lead-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes.
Applications
DDR Memory Clock Source
Pin Configuration and Selector Guide appear at end of data sheet.
Typical Operating Circuits
VCC 0.1F 0.01F
OUTP 0.1F 0.01F
VCC
OUTP 50
DS4266
OE GND OUTN
100 OE GND
DS4266
50 OUTN
PECL_BIAS VCC - 2.0V
LVDS OPTION
LVPECL OPTION
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
DDR Clock Oscillator DS4266
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .......................................-0.3V, +4V Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range ...............................-55C to +85C Soldering Temperature Profile (3 passes max of reflow) ......................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Operating Voltage Range Operating Current Output Frequency Oscillator Startup Time Frequency Stability Frequency Stability Over Temperature with Initial Tolerance Initial Tolerance Frequency Change Due to VCC Frequency Change Due to Load Variation Aging (15 Years) SYMBOL VCC ICC_D ICC_PU ICC_PI f OUT t STARTUP fTOTAL fTEMP f INITIAL f VCC fLOAD fAGING Integrated phase RMS; 12kHz to 5MHz, VCC = 3.3V, TA = +25C Jitter JRMS Integrated phase RMS; 12kHz to 20MHz, VCC = 3.3V, TA = +25C Integrated phase RMS; 12kHz to 80MHz, VCC = 3.3V, TA = +25C Input-Voltage High (OE) Input-Voltage Low (OE) Input Leakage (OE) VIH VIL ILEAK (Note 1) (Note 1) GND OE VCC 0.7 x VCC 0 -50 (Note 2) Over temperature range, aging, load, supply, and initial tolerance (Note 3) VCC = 3.3V VCC = 3.3V, TA = +25C VCC = 3.3V 5% 10% variation in termination resistance -7 0.7 0.7 1.0 VCC 0.3 x VCC +5.0 V V A ps -50 -35 20 -3 1 +7 +3 fNOM (Note 1) LVDS, output loaded or unloaded LVPECL, output unloaded LVPECL, output load 50 at VCC - 2.0V CONDITIONS MIN 3.135 TYP 3.3 52 49 74 fNOM 50 +50 +35 MAX 3.465 75 70 100 MHz ms ppm ppm ppm ppm/V ppm ppm mA UNITS V
2
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DDR Clock Oscillator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER LVDS Output High Voltage Output Low Voltage Differential Output Voltage Output Common-Mode Voltage Variation Change in Differential Magnitude or Complementary Inputs Offset Output Voltage Differential Output Impedance Output Current Output Rise Time (Differential) Output Fall Time (Differential) Duty Cycle Propagation Delay from OE Going Low to Logical 1 at OUTP Propagation Delay from OE Going High to Output Active LVPECL Output High Voltage Output Low Voltage Differential Voltage Rise Time Fall Time Duty Cycle Propagation Delay from OE Going Low to Output High Impedance Propagation Delay from OE Going High to Output Active VOH VOL VDIFF_PECL tR-PECL tF-PECL DCYCLE_PECL t PAZ t PZA 48 Output connected to 50 at VCC - 2.0V Output connected to 50 at VCC - 2.0V Output connected to 50 at VCC - 2.0V at PECL_BIAS at PECL_BIAS at PECL_BIAS VCC 1.085 VCC 1.825 0.595 0.710 200 200 52 200 200 VCC 0.88 VCC 1.62 V V V ps ps % ns ns VOHLVDSO VOLLVDSO |VODLVDSO| VLVDSOCOM |VODLVDSO| VOFFLVDSO R OLVDSO L VSSLVDSO LLVDSO tRLVDSO tFLVDSO DCYCLE_LVDS t PA1 t P1A OUTN or OUTP shorted to ground and measure the current in the shorting path OUTN or OUTP shorted together 20% to 80% 80% to 20% 48 6.5 175 175 52 200 200 ps ps % ns ns 100 100 100 100 100 100 differential load (Note 1) differential load (Note 1) differential load differential load differential load differential load (Note 1) 1.125 80 0.925 250 425 150 25 1.275 140 40 mA 1.475 V V mV mV mV V SYMBOL CONDITIONS MIN TYP MAX UNITS
DS4266
Note 1: All voltages referenced to ground. Note 2: AC parameters are guaranteed by design and not production tested. Note 3: Frequency stability is calculated as: fTOTAL = fTEMP + fVCC x (3.3 x 5%) + fLOAD + fAGING.
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DDR Clock Oscillator DS4266
Single-Sideband Phase Noise at fO = fNOM
fM = 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 20MHz SINGLE-SIDEBAND PHASE NOISE AT fO = fNOM (dBc/Hz) 266MHz -65 -95 -113 -113 -118 -137 -149 -153
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
FREQUENCY vs. TEMPERATURE
15 13 10 8 5 3 0 -3 -5 -8 -10 -13 -15 -18 -20 -40 -20 0 20 40 60 80 TEMPERATURE (C)
DS4266 toc01
OPERATING CURRENT vs. OPERATING VOLTAGE
+40C +70C +25C
DS4266 toc02
55 +85C 53 ICC (mA)
fOUT DEVIATION (ppm)
50
0C 48 -40C 45 3.135 3.185 3.235 3.285 3.335 3.385 3.435 VCC (V)
Pin Description
PIN 1 2, 7-10 3 4 5 6 -- NAME OE N.C. GND OUTP OUTN VCC EP No Connection. Must be floated. Ground Positive Output for LVPECL or LVDS Negative Output for LVPECL or LVDS Supply Voltage Exposed Paddle. Do not connect this pad or place exposed metal under the pad. FUNCTION Active-High Output Enable. Has an internal pullup 100k resistor.
4
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DDR Clock Oscillator DS4266
VCC
X1 THREESTATE PHASE DET LC-VCO FILTER /n OUTSELN OUTDRV
OE OUTP
X2
OUTN
DS4266
/m
GND
Figure 1. Functional Diagram
Detailed Description
The DS4266 consists of a fundamental-mode crystal and synthesizer IC packaged in a 5mm x 3.2mm x 1.49mm, 10-pin LCCC ceramic package. The device produces a frequency output of 266.00MHz. Two differential output types are available: LVDS and LVPECL. The device output can be enabled or disabled through the OE signal input. When the OE signal is low, LVPECL
outputs go to the PECL_BAS level of VCC - 2.9V, while the LVDS outputs are a logical 1. See Figures 2 and 3 for LVDS and LVPECL output timing diagrams.
Additional Information
For more available frequencies in the DS4-XO family, refer to the DS4125 data sheet at www.maximic.com/DS4125.
0.7 x VCC OE 0.3 x VCC tP1A tPA1 OE
0.7 x VCC 0.3 x VCC tPZA tPAZ PECL_BIAS
OUTP OUTP OUTN PECL_BIAS
OUTN
PECL_BIAS
PECL_BIAS
Figure 2. LVDS Output Timing Diagram When OE Is Enabled and Disabled
Figure 3. LVPECL Output Timing Diagram When OE Is Enabled and Disabled
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DDR Clock Oscillator DS4266
Selector Guide
PART DS4266D+ DS4266P+ FREQUENCY (NOM) (MHz) 266 266 FREQUENCY STABILITY (ppm) 50 50 OUTPUT TYPE LVDS LVPECL TOP MARK 66D 66P
+Denotes a lead-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both leadbased and lead-free soldering processes.
Pin Configuration
TOP VIEW
N.C. N.C.
Chip Information
SUBSTRATE CONNECTED TO GROUND PROCESS: BiPOLAR SiGe
+
OE 1 6 VCC
Thermal Information
THETA-JA (C/W) 90
N.C.
2
DS4266
5
OUTN
GND
3
*EP
4
OUTP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
N.C.
N.C.
PACKAGE TYPE (5.00mm x 3.20mm x 1.49mm)
*EXPOSED PAD
PACKAGE CODE --
DOCUMENT NO. 56-G5032-002
10 LCCC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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